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3769f 1 fo r mor e ??e? ictry ? power loss (w) efficiency (%) l tc3769 60v low i q synch r onous boost cont r oller fea t ure s descrip t ion n synchronous operation for highest efficiency and reduced heat dissipation n wide v in range: 4.5v to 60v (65v abs max); operates down to 2.3v after start - up n output v oltage up to 60v n 1% 1.200v reference v oltage n r sense or inductor dcr current sensing n 100 % dut y cycl e capabilit y fo r synchronou s mosfet n low quiescent current: 28a n phase - lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n power good output v oltage monitor n low shutdown current: 4a n interna l ld o power s gat e driv e fro m vbia s o r ex t v cc n thermally enhanced low profile 24 - pin 4mm 4mm qfn package and 20 - lead tssop package a pplica t ions n industrial n automotive n medical n milita r y the l t c 3769 ? is a high per formance single output syn - chronous boost converter controller that drives an all n - channel power mosfet stage. synchronous rectifica - tion increases efficienc y , reduces power losses and eases thermal requirements, simplifying high power boost ap - plications. the 28a no - load quiescent current extends operating run time in batte r y - powered systems. a 4.5v to 60v input supply range encompasses a wide range of system a r chitectures and batte r y chemistries. when biased from the output of the boost converter or another auxilia r y suppl y , the l tc3769 can operate from an input supply as low as 2.3v after start - up. the operating frequency can be set within a 50khz to 900khz range or synchronized to an external clock using the internal pll. the ss pin ramps the output voltage during start - up. the pllin/mode pin selects burst mode ? operation, pulse - skipping mode or fo r ced continuous mode at light loads. l , l t , l tc, l tm, burst mode, o p ti - loo p , linear t echnology and the linear logo are registered trademarks of linear t echnology corporation. all other trademarks are the property of their respective owners. protected by u. s. patents, including 5408150, 5481178, 5705919, 5929620, 6177787, 6498466, 6580258, 6611131. typica l a pplica t ion 120 w , 12v to 24v/5a synchronous boost converter efficiency and power loss vs output current v in 4.5v to 60v 4mfi 3.3h v out 24v/5a 100 10 down to 2.3v a f ter s t a r t - up if 22f 220f vbias 90 efficiency 1 vbias is powered from v out 10nf 15nf 8.66k run ss ith ltc3769 sense + sense ? bg v out follows v in for v in > 24v 80 70 power loss 0.1 100pf pllin/mode freq ovmode tg sw boost 0. 1 f 60 50 40 0.0001 0.001 0.01 0.1 1 10 0.01 0.001 ilim pgood gnd intv cc vfb ex t v cc 4.7f 232k 12.1k output current (a) 3769 t a01b 3769 t a01a
3769f 2 fo r mor e ??e? ictry ? l tc3769 24 23 22 21 20 19 1 25 gnd 18 2 17 3 16 4 15 5 14 6 13 7 8 9 10 11 12 top view ilim 1 20 pgood in t v cc 2 19 vbias freq 3 18 extv cc gnd 4 17 intv cc pllin/mode 5 21 16 bg run 6 gnd 15 boost ss 7 14 tg sense ? 8 13 sw sense + 9 12 ovmode vfb 10 11 ith freq gnd pllin/mode gnd run ss gnd ext v cc in t v cc bg boost tg a bsolu t e maximu m r a t ings (notes 1, 3) v b i a s ........................................................ ? 0 . 3 v to 65 v b oo s t ....................................................... . ? 0 . 3 v to 7 1 v s w ................................................................ ? 5 v to 65 v r u n ............................................................. ? 0 . 3 v to 8 v m a x imu m c u r r e n t s o u rc e d i n t o p i n f r o m s o u rc e > 8 v ............................................. . 1 0 0 a p g o o d , pl l i n / m od e ................................. ? 0 . 3 v t o 6 v i n t v c c , ( b oos t - s w ) ................................. . ? 0 . 3 v t o 6 v e x t v c c ...................................................... ? 0 . 3 v to 1 4 v sens e + , sens e ? ........................................ ? 0 . 3 v t o 65 v ( s e ns e + - s e ns e ? ) ........................................... . ? 0 . 3 v t o 0 . 3v i l i m , s s , i t h , f r e q , p ha sm d , v f b ..... ? 0 . 3 v t o i n t v cc o p e r at i ng ju n c t io n t e m p e r a t u r e range ( n o te 2 ) ....................................... . ? 5 5 c t o 1 50 c s t o r age t e m p e r a t u r e range .................. ? 6 5 c to 1 50 c l e ad t e m p e r a t u r e ( s old e r in g , 1 0 se c ) s s o p ........ 3 0 0 c pin c on f igura t ion top view vbias pgood ilim nc in t v cc nc sw ovmode ith vfb sense + sense ? fe p ackage 20 - lead plastic tssop t jmax = 150c, ? ja = 38c/w exposed p ad (pin 21) is gnd, must be soldered to pcb uf p ackage 24- lead (4mm 4mm) plastic qfn t jmax = 150c, ? ja = 47c/w exposed p ad (pin 25) is gnd, must be soldered to pcb o r d e r in f or m a t ion lead free finish t ape and reel p a r t marking* p ackage descri p tion temper a ture range l tc3769euf#pbf l tc3769euf#trpbf 3769 24-lead (4mm ? 4mm) plastic qfn ? 40c to 125c l tc3769iuf#pbf l tc3769iuf#trpbf 3769 24-lead (4mm ? 4mm) plastic qfn ? 40c to 125c l tc3769huf#pbf l tc3769huf#trpbf 3769 24-lead (4mm ? 4mm) plastic qfn ? 40c to 150c l tc3769mpuf#pbf l tc3769mpuf#trpbf 3769 24-lead (4mm ? 4mm) plastic qfn ? 55c to 150c l tc3769efe#pbf l tc3769efe#trpbf l tc3769fe 20- lead plastic ssop ? 40c to 125c l tc3769ife#pbf l tc3769ife#trpbf l tc3769fe 20- lead plastic ssop ? 40c to 125c l tc3769hfe#pbf l tc3769hfe#trpbf l tc3769fe 20- lead plastic ssop ? 40c to 150c l tc3769mpfe#pbf l tc3769mpfe#trpbf l tc3769fe 20- lead plastic ssop ? 55c to 150c consul t l t c marketin g fo r part s specifie d wit h wide r operatin g temperatur e ranges . *th e temperatur e grad e i s identifie d b y a labe l o n th e shippin g containe r . for more information on lead free part marking, go to: http://www.ictry.cn/ic/122.html for more information on tape and reel specifications, go to: http://www.ictry.cn/ic/124.html
3769f 3 fo r mor e ??e? ictry ? l tc3769 vbias chip bias v oltage operating range 4.5 60 v v in sense pins common mode range (boost converter input supply v oltage) 2.3 60 v v out regulated output v oltage range v in 60v v v fb regulated feedback v oltage i th = 1.2v (note 4) l 1.188 1.200 1.212 v feedback current (note 4) 5 50 na reference line v oltage regulation vbias = 6v to 60v 0.002 0.02 %/v output v oltage load regulation (note 4) measured in ser vo loop; i th v oltage = 1.2v to 0.7v l 0.01 0.1 % measured in se r vo loop; i th v oltage = 1.2v to 2v l ? 0.01 ? 0.1 % error amplifier t ransconductance i th = 1.2v 2 mmho i q input dc supply current (vbias pin) pulse - skippin g o r fo r ce d continuou s mode sleep mode shutdown (note 5) run = 5 v ; v fb = 1.25v (no load) run = 5 v ; v fb = 1.25v (no load) run = 0v 0.9 28 45 4 10 ma a a sw pin current v sw = 12v ; v boost = 16.5 v ; freq = 0 v , fo r ced continuous or pulse - skipping mode 700 a uvlo int v cc unde r voltage lockout thresholds v in t vcc ramping up v in t vcc ramping down l l 4.1 4.3 3.6 3.8 v v v run run pin on threshold v run rising l 1.18 1.28 1.38 v run pin hysteresis 100 mv run pin hysteresis current v run > 1.28v 4.5 a run pin current v run < 1.28v 0.5 a soft - start charge current v ss = gnd 7 10 13 a v sense(max) maximum current sense threshold v fb = 1.1 v , i lim = int v cc v fb = 1.1 v , i lim = float v fb = 1.1 v , i lim = gnd l l l 90 100 110 68 75 82 42 50 56 mv mv mv sense + pin current v fb = 1.1 v , i lim = float 200 300 a sense ? pin current v fb = 1.1 v , i lim = float 1 a t op gate rise t ime c load = 3300pf (note 6) 20 ns t op gate fall t ime c load = 3300pf (note 6) 20 ns bottom gate rise t ime c load = 3300pf (note 6) 20 ns bottom gate fall t ime c load = 3300pf (note 6) 20 ns t op gate pull - up resistance 1.2 t op gate pull - down resistance 1.2 bottom gate pull - up resistance 1.2 bottom gate pull - down resistance 1.2 t op gate off to bottom gate on switch -on delay t ime c load = 3300pf (each driver) 30 ns bottom gate off to t op gate on switch -on delay t ime c load = 3300pf (each driver) 30 ns maximum bg duty factor 96 % t on(min) minimum bg on- t ime (note 7) 110 ns e lec t rica l c harac t eris t ic s the l denotes the specifications which apply over the specified operating junction temperature range, othe r wise specifications are at t a = 25c, vbias = 12 v , unless othe r wise noted (note 2). symbol p arameter conditions min t yp max units main control loop
3769f 4 fo r mor e ??e? ictry ? l tc3769 e lec t rica l c harac t eris t ic s the l denotes the specifications which apply over the specified operating junction temperature range, othe r wise specifications are at t a = 25c, vbias = 12 v , unless othe r wise noted (note 2). symbol p arameter conditions min t yp max units in t v cc linear regulator internal v cc v oltage 6v < v bias < 60v , v ext vcc = 0 5.2 5.4 5.6 v in t v cc load regulation i cc = 0ma to 50ma 0.5 2 % internal v cc v oltage 6v < v ext vcc < 13v 5.2 5.4 5.6 v in t v cc load regulation i cc = 0ma to 40ma, v ext vcc = 8.5v 0.5 2 % ext v cc switchover v oltage ex t v cc ramping positive l 4.5 4.8 5 v ext v cc hysteresis 250 mv oscillator and phase - locked loop programmable frequency r freq = 25k r freq = 60k r freq = 100k 105 335 400 465 760 khz khz khz f low lowest fixed frequency v freq = 0v 320 350 380 khz highest fixed frequency v freq = int v cc 488 535 585 khz synchronizable frequency pllin/mode = external clock l 75 850 khz pgood output pgood v oltage low i pgood = 2ma 0.2 0.4 v pgood leakage current v pgood = 5v 1 a pgood t rip level v f b wit h respec t t o se t regulate d v oltage v fb ramping negative hysteresis ? 12 ? 10 ? 8 2.5 % % v fb ramping positive hysteresis 8 10 12 2.5 % % pgood delay pgood going high to low 45 s ov protection threshold v fb ramping positive, ovmode = 0v 1.296 1.32 1.344 v boost charge pump boost charge pump available output current v sw = 12 v ; v boost ? v sw = 4.5 v ; freq = 0 v , fo r ced continuous or pulse - skipping mode 55 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the l tc3769 is tested under pulsed load conditions such that t j t a . the l tc3769e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the ? 40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the l tc3769i is guaranteed over the ? 40c to 125c operating junction temperature range, the l tc3769h is guaranteed over the ? 40c to 150c operating temperature range and the l tc3769mp is tested and guaranteed over the full ? 55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. th e junctio n temperatur e (t j , i n c ) i s calculate d fro m th e ambient temperatur e (t a , in c ) and power dissipatio n (p d , in w atts) according to the formula: t j = t a + (p d ? ? ja ), where ? ja = 47c/w for the qfn package and ? ja = 38c/w for the tssop package. note 3: this ic includes overtemperature protection that is intended to protect the device during momenta r y overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the l tc3769 is tested in a feedback loop that se r vos v fb to the output of the error amplifier while maintaining i th at the midpoint of the current limit range. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequenc y . note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: see minimum on- t ime considerations in the applications information section.
3769f 5 fo r mor e ??e? ictry ? l tc3769 typica l p er f or m anc e c harac t eris t ic s t a = 25c unless othe r wise noted. power loss (w) power loss (w) efficiency (%) efficiency (%) efficiency (%) 100 90 80 70 60 50 40 30 efficiency and power loss vs output current v in = 12v v out = 24v figure 8 circuit 10 1 0.1 0.01 100 90 80 70 60 efficiency and power loss vs output current efficiency power loss 10 1 0.1 20 fcm efficiency fcm loss 0.001 50 v in = 12v 0.01 10 0 0.01 pulse - skipping efficiency pulse - skipping loss 0.1 1 10 0.0001 40 0.0001 0.001 0.01 v out = 24v figure 8 circuit 0.1 1 10 0.001 output current (a) 3769 g01 output current (a) 3769 g02 100 99 98 97 96 efficiency vs input v oltage i load = 2a figure 8 circuit v out = 12v v out = 24v load step 2a/div inductor current 5a/div v out 500m v /div load step forced continuous mode load step 2a/div inductor current 5a/div v out 500m v /div load step burst mode operation 95 v in = 12v 94 v out = 24v 200s/div 3769 g04 v in = 12v v out = 24v 200s/div 3769 g05 93 0 5 10 15 20 25 input vo l t age (v) load step from 200ma to 2.5a figure 8 circuit load step from 200ma to 2.5a figure 8 circuit 3769 g03 load step 2a/div inductor current load step pulse - skipping mode forced continuous mode inductor currents at light load soft start - up 5a/div burst mode oper a tion 5a/div v out v out 500m v /div pulse - skipping mode 5 v /div v in = 12v v out = 24v 200s/div 3769 g06 v in = 12v v out = 24v 5s/div 3769 g07 v run 5 v /div load step from 200ma to 2.5a figure 8 circuit i load = 200a 0v figure 8 circuit v in = 12v v out = 24v figure 8 circuit 20ms/div 3769 g08
l tc3769 typica l p er f or m anc e c harac t eris t ic s t a = 25c unless othe r wise noted. 3769f 6 fo r mor e informatio n ww w . li n ea r . c o m / l t c 376 9 v in = 12v v in = 12v v fb = 1.25v run = gnd in t v cc rising in t v cc f alling shutdown current (a) regulated feedback voltage (v) intv cc voltage (v) quiescent current (a) soft - start current (a) intv cc voltage (v) shutdown current (a) run pin voltage (v) 1.212 1.209 1.206 1.203 1.200 1.197 1.194 1.191 1.188 regulated feedback v oltage vs t emperature 11.0 10.5 10.0 9.5 9.0 soft - start pull - up current vs t emperature 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 shutdown current vs t emperature ?60 ? 35 ? 10 15 40 65 90 115 140 ?60 ? 35 ? 10 15 40 65 90 115 140 ?60 ? 35 ? 10 15 40 65 90 115 140 temperature (c) 3769 g09 temperature (c) 3769 g10 temperature (c) 3769 g11 12.5 10.0 7.5 5.0 2.5 shutdown current vs input v oltage v in = 12v quiescent current vs t emperature 50 45 40 35 30 25 20 15 1.40 1.35 1.30 1.25 1.20 1.15 shutdown (run) threshold vs t emperature run rising run f alling 0 5 10 15 20 25 30 35 40 45 50 55 60 65 10 ?60 ? 35 ? 10 15 40 65 90 115 140 1.10 ? 60 ? 35 ? 10 15 40 65 90 115 140 input voltage (v) 3769 g12 temperature (c) 3769 g13 temperature (c) 3769 g14 4.4 4.3 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 unde r voltage lockout threshold vs t emperature 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 int v cc line regulation ? 60 ? 35 ? 10 15 40 65 90 115 140 0 5 10 15 20 25 30 35 40 45 50 55 60 65 temperature (c) 3769 g15 input voltage (v) 3769 g16
l tc3769 typica l p er f or m anc e c harac t eris t ic s t a = 25c unless othe r wise noted. 3769f 7 fo r mor e informatio n ww w . li n ea r . c o m / l t c 376 9 v in = 12v ex t v cc = 0v ex t v cc = 6v in t v cc ex t v cc rising ex t v cc f alling freq = in t v cc freq = gnd freq = gnd v sense = 12v i lim = float sense + pin sense ? pin 80 60 40 20 0 in t v cc vo l t age (v) oscillator frequency (khz) sense current (a) extv cc and intv cc voltage (v) maximum current sense voltage (mv) sense current (a) sense current (a) frequency (khz) 5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00 int v cc vs int v cc load current 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 ex t v cc switchover and in t v cc v oltages vs t emperature 600 550 500 450 400 350 300 oscillator frequency vs t emperature 0 20 40 60 80 100 120 140 160 180 200 ?60 ? 35 ? 10 15 40 65 90 115 140 ? 60 ? 35 ? 10 15 40 65 90 115 140 in t v cc load current (ma) 3769 g17 temper a ture (c) 3769 g18 temper a ture (c) 3769 g19 360 358 356 354 352 350 348 346 344 342 340 oscillator frequency vs input v oltage 120 100 ?20 ?40 ? 60 maximum current sense threshold vs i th v oltage pulse - skipping mode burst mode operation i lim = gnd i lim = float i lim = intv cc forced continuous mode 260 240 220 200 180 160 140 120 100 80 60 40 20 0 sense pin input current vs t emperature 5 10 15 20 25 30 35 40 45 50 55 60 65 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ? 60 ? 35 ? 10 15 40 65 90 115 140 input voltage (v) 3769 g20 i th voltage (v) 3769 g21 temper a ture (c) 3769 g22 260 240 220 200 180 160 140 120 100 80 60 40 sense pin input current vs i th v oltage v sense = 12v i lim = in t v cc i lim = flo a t sense + pin i lim = gnd i lim = in t v cc i lim = flo a t 260 240 220 200 180 160 140 120 100 80 60 40 sense pin input current vs v sense v oltage sense + pin i lim = intv cc i lim = float i lim = gnd i lim = intv cc i lim = float 20 sense ? pin 0 i lim = gnd 20 sense ? pin 0 i lim = gnd 0 0.5 1 1.5 2 2.5 3 5 10 15 20 25 30 35 40 45 50 55 60 65 i th vo l t age (v) 3769 g23 v sense common mode voltage (v) 3769 g24
l tc3769 typica l p er f or m anc e c harac t eris t ic s t a = 25c unless othe r wise noted. 3769f 8 fo r mor e informatio n ww w . li n ea r . c o m / l t c 376 9 maximum current sense vo l t age (mv) charge pump charging current (a) charge pump charging current (a) 120 100 80 60 40 20 maximum current sense threshold vs duty cycle i lim = in t v cc i lim = flo a t i lim = gnd charge pump charging current vs operating frequency 80 t = ? 60c 70 60 t = ? 45c 50 t = 25c 40 t = 130c 30 t = 155c 20 10 charge pump charging current vs switch v oltage 70 freq = gnd 60 freq = intv cc 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 0 50 150 250 350 450 550 650 750 0 5 15 25 35 45 55 65 du t y cycle (%) 3769 g25 oper a ting frequency (khz) 3769 g26 switch voltage (v) 3769 g27 pin func t ions (qfn/tssop) vbias (pin 1/pin 19): main supply pin. it is normally tied to the input supply v in or to the output of the boost converte r . a bypass capacitor should be tied between this pin and the signal ground pin. the operating voltage range on this pin is 4.5v to 60v (65v abs max). pgood (pin 2/pin 20): power good indicato r . open - drain logic output that is pulled to ground when the output volt - age is more than 10% away from the regulated output voltage. t o avoid false trips the output voltage must be outside the range for 45s before this output is activated. ilim (pin 3/pin 1): current comparator sense v oltage range input. this pin is used to set the peak current sense voltage in the current comparato r . connect this pin to sgnd, leave floating or connect to in t v cc to set the peak current sense voltage to 50m v , 75mv or 100m v , respectivel y . in t v c c (pin s 5 , 22/pin s 2 , 17) : outpu t o f interna l 5.4 v ldo. power supply for control ci r cuits and gate drivers. de - couple pin 22/17 to gnd with a minimum 4.7f low esr ceramic capacito r . connect pin 5/2 to pin 22/17 with a trace on the printed ci r cuit board. freq (pin 7/pin 3): frequency control pin for the internal vco. connecting the pin to gnd fo r ces the vco to a fixed low frequency of 350khz. connecting the pin to in t v cc fo r ces the vco to a fixed high frequency of 535khz. the frequency can be programmed from 50khz to 900khz by connecting a resistor from the freq pin to gnd. the resistor and an internal 20a sou r ce current create a volt - age used by the internal oscillator to set the frequenc y . alternativel y , this pin can be driven with a dc voltage to va r y the frequency of the internal oscillato r . gnd (pin 8, 10, 24, exposed pad pin 25/ pin 4, exposed pad pin 21): ground. all ground pins must be connected and the exposed pad must be soldered to the pcb for rated electrical and thermal per formance. pllin/mode (pin 9/pin 5): external synchronization input to phase detector and fo r ced continuous mode input. when an external clock is applied to this pin, the phase - locked loop will fo r ce the rising edge of bg to be synchronized with the rising edge of the external clock. when an external clock is applied to this pin, the ovmode pin is used to determine how the l tc3769 operates at light load. when not synchronizing to an external clock, this
3769f 9 fo r mor e informatio n ww w . li n ea r . c o m / l t c 376 9 l tc3769 pin func t ions (qfn/tssop) input determines how the l tc3769 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. t ying this pin to in t v cc fo r ces continuous inductor current operation. t ying this pin to a voltage greater than 1.2v and less than in t v cc ? 1.3v selects pulse - skipping operation. this can be done by adding a 100k resistor between the pllin/ mode pin and in t v cc . run (pin 11/pin 6): run control input. for cing this pin below 1.28v shuts down the controlle r . for cing this pin below 0.7v shuts down the entire l tc3769, reducing quiescen t curren t t o approximatel y 4a . a n external resistor divider connected to v in can set the threshold for converter operation. once running, a 4.5a current is sou r ced from the run pin allowing the user to program hysteresis using the resistor values. ss (pin 12/pin 7): output soft - start input. a capacitor to ground at this pin sets the ramp rate of the output voltage during start - up. sense + (pi n 13/pi n 9) : positiv e curren t sens e comparator input. the (+) input to the current comparator is normally connected to the positive terminal of a current sense resi s - to r . the current sense resistor is normally placed at the input of the boost controller in series with the inducto r . this pin also supplies power to the current comparato r . the common mode voltage range on sense + and sense ? pins is 2.3v to 60v (65v abs max). sense ? (pi n 14/pi n 8) : negativ e curren t sens e comparator input. the ( ? ) input to the current comparator is normally connected to the negative terminal of a current sense resistor connected in series with the inducto r . vfb (pin 15/pin 10): error amplifier feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider connected across the output. ith (pin 16/pin 11): current control threshold and error amplifier compensation point. the voltage on this pin sets the current trip threshold. ovmode (pin 17/pin 12): ove r voltage mode selection input. this pin is used to select how the l tc3769 operates when the output feedback voltage (v fb ) is ove r voltage (>110% of its normal regulated point of 1.2v). it is also used to determine the light - load mode of operation when the l tc3769 is synchronized to an external clock through the pllin/mode pin. when ovmode is tied to ground, ove r voltage protection is enabled and the top mosfet gate (tg) is turned on continuously until the ove r voltage condition is cleared. when ovmode is grounded, the l tc3769 operates in fo r ced continuous mode when synchronized. there is an internal weak pull - down resistor that pulls the ovmode pin to ground when it is left floating. when ovmode is tied to in t v cc , ove r voltage protection is disabled and tg is not fo r ced on during an ove r volt - age event. instead, the state of tg is determined by the mode of operation selected by the pllin/mode pin and the inductor current. see the operation section for more details. when ovmode is tied to in t v cc , the l tc3769 operates in pulse - skipping mode when synchronized. sw (pin 18/pin 13): switch node. connect to the sou r ce of the synchronous n - channel mosfe t , the drain of the main n - channel mosfet and the inducto r . tg (pin 19/pin 14): t op gate. connect to the gate of the synchronous n - channel mosfe t . boost (pin 20/pin 15): floating power supply for the synchronous n - channel mosfe t . bypass to sw with a capacitor and supply with a schottky diode connected to in t v cc . bg (pin 21/pin 16): bottom gate. connect to the gate of the main n - channel mosfe t . e x t v c c ( p i n 23 / p i n 18 ) : e x t e r n a l p o w e r i npu t t o a n i n t e r n a l ld o connecte d t o in t v cc . thi s ld o supplie s in t v c c powe r , bypassing the internal ldo powered from v bias whenever ext v cc is higher than 4.7 v . see ex t v cc connection in the applications information section. do not float or exceed 14v on this pin. connect to ground if not used.
l tc3769 3769f 10 fo r mor e ??e? ictry ? bloc k diagra m boost s q intv cc d b freq 20a vco clk r 0.425v + shdn sleep switching logic and charge pump intv cc tg c b sw bg v out c out pgnd ? pfd + i cmp i rev l ovmode pllin/ mode ilim vbias extv cc 5m 100k 5.4v sync det current limit 5.4v shdn ? + 2.8v 0.7v slope comp sens lo + ? ? 2mv 2.3v ea ov 1.2v ss 1.32v sense ? sense + vfb r sense v in c in ldo en ldo en ? + 3.8v 0.5a/ 4.5a ith c c r c + 4.8v ? intv cc sgnd shdn run 11v sens lo 10a ss 1.32v + ? vfb + 1.08v ? c ss pgood 3769 bd c c2
3769f 11 fo r mor e ??e? ictry ? l tc3769 o pera t ion main control loop the l tc3769 uses a constant - frequenc y , current mode step - u p a r chitecture . durin g norma l operation , each external bottom mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparato r , icm p , resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier ea. the error amplifier compares the output voltage feedback signal at the vfb pin (which is generated with an external resistor divider connected across the output voltage, v out , to ground), to the internal 1.200v reference voltage. in a boost converte r , the required inductor current is determined by the load current, v in and v out . when the load current increases, it causes a slight decrease in vfb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current in each channel matches the new requirement based on the new load current. after the bottom mosfet is turned off each cycle, the top mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparato r , i rev , or the beginning of the next clock cycle. in t v cc /ex t v cc power power for the top and bottom mosfet drivers and most other internal ci r cuit r y is derived from the in t v cc pin. when the ext v cc pin is tied to a voltage less than 4.8 v , the vbias ldo (low dropout linear regulator) supplies 5.4v from vbias to in t v cc . if ext v cc is taken above 4.8 v , the vbias ldo is turned off and an ext v cc ldo is turned on. once enabled, the ext v cc ldo supplies 5.4v from ex t v cc to in t v cc . using the ext v cc pin allows the in t v cc power to be derived from an external sou r ce, thus removing the power dissipation of the vbias ldo. shutdown and start - up (run and ss pins) the l tc3769 can be shut down using the run pin. pulling this pin below 1.28v shuts down the main control loops. pulling this pin below 0.7v disables the controller and most internal ci r cuits, including the in t v cc ldos. in this state, the l tc3769 draws only 4a of quiescent current. note: do not apply a heavy load to the boost converter for an extended time while the l tc3769 is in shutdown. the top mosfet is turned off during shutdown and the output load may cause excessive dissipation in the body diode. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance sou r ce, do not exceed the absolute maximum rating of 8 v . the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v in ), as long as the maxi - mum current into the run pin does not exceed 100a. an external resistor divider connected to v in can set the threshold for converter operation. once running, a 4.5a current is sou r ced from the run pin allowing the user to program hysteresis using the resistor values. the start - up of the controlle r? s output voltage v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 1.2v internal reference, the l tc3769 regulates the vfb voltage to the ss pin voltage instead of the 1.2v reference. this allows the ss pin to be used to program a soft - start by connecting an external capacitor from the ss pin to sgnd. an internal 10a pull - up current charges this capacitor creating a voltage ramp on the ss pin. as the ss voltage rises linearly from 0v to 1.2v (and beyond up to in t v cc ), the output voltage rises smoothly to its final value. light load current operation ? burst mode operation, pulse - skipping or continuous conduction (pllin/mode pin) the l tc3769 can be enabled to enter high efficiency burst mod e operation , constant - frequenc y , pulse - skipping mode or fo r ced continuous conduction mode at low load currents. t o select burst mode operation, tie the pllin/mode pin to ground (e.g., sgnd). t o select fo r ced continuous operation, tie the pllin/mode pin to in t v cc . t o select pulse - skipping mode, tie the pllin/ mode pin to a dc voltage greater than 1.2v and less than in t v cc ? 1.3 v . when the controller is enabled for burst mode opera - tion, the minimum peak current in the inductor is set to
3769f 12 fo r mor e ??e? ictry ? l tc3769 o pera t ion approximately 30% of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the required current, the error amplifier ea will decrease the voltage on the ith pin. when the ith voltage drops below 0.425 v , the internal sleep signal goes high (enabling sleep mode) and both external mosfe t s are turned off. in sleep mode much of the internal ci r cuit r y is turned off and the l tc3769 draws only 28a of quiescent current. in sleep mode the load current is supplied by the output capacito r . as the output voltage decreases, the e a ? s output begins to rise. when the output voltage drops enough, the sleep signal goes low and the controller resumes normal operation by turning on the bottom external mosfet on the next cycle of the internal oscillato r . when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse curren t comparato r ( i rev ) turn s of f th e to p externa l mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous current operation. in fo r ced continuous operation or when clocked by an external clock sou r ce to use the phase - locked loop (see the frequency selection and phase - locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cu r - rent is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. howeve r , continuous operation has the advantages of lower output voltage ripple and less inte r ference to audio ci r cuit r y , as it maintains constant - frequency operation independent of load current. whe n th e pllin/mod e pi n i s connecte d fo r pulse - skipping m o de, t he l tc 3 7 6 9 o pe r a t es in p w m pul se - s ki ppi ng mo d e at light loads. in this mode, constant - frequency operation is maintained down to approximately 1% of designed maximum output current. at ve r y light loads, the current comparator icmp may remain tripped for several cycles and fo r ce the external bottom mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like fo r ced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf inte r ference as compared to burst mode operation. it provides higher low current efficiency than fo r ced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase - locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade - off between efficiency and component size. low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the l tc3769 ? s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock sou r ce, the freq pin can be tied to sgnd, tied to i n t v c c , or pr o gr a mme d t hr o ugh a n e xt e r n al r e si s to r . t yi ng freq to sgnd selects 350khz while tying freq to in t v cc s e l e c t s 535 k h z . p l a c i n g a r e s i s t o r b e t w ee n f r e q a n d s g n d allows the frequency to be programmed between 50khz and 900khz, as shown in figure 7. a phase - locked loop (pll) is available on the l tc3769 to synchronize the internal oscillator to an external clock sou r ce that is connected to the pllin/mode pin. the l tc3769 ? s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input so that the turn - on of the external bottom mosfet is 180 out - of - phase to the rising edge of the external clock sou r ce. when syn - chronized, the l tc3769 will operate in fo r ced continuous mode of operation if the ovmode pin is grounded. if the ovmode pin is tied to in t v cc , the l tc3769 will operate in pulse - skipping mode of operation when synchronized. the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequenc y , the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clock ? s to the rising edge of bg1. the ability to prebias the loop filter allows the pll to lock - in rapidly without deviating far from the desired frequenc y .
3769f 13 fo r mor e ??e? ictry ? l tc3769 o pera t ion the typical capture range of the l tc3769 ? s pll is from approximately 55khz to 1mhz, and is guaranteed to lock to an external clock sou r ce whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). the recommended maximum amplitude for low level and minimum amplitude for high level of external clock are 0v and 2.5 v , respectivel y . operation when v in > regulated v out when v in rises above the regulated v out voltage, the boost controller can behave differently depending on the mode, inductor current and v in voltage. in fo r ced continuous mode, the control loop works to keep the top mosfet on continuousl y onc e v i n rise s abov e v out . th e interna l charge pump delivers current to the boost capacitor to maintain a sufficiently high tg voltage. the amount of current the charge pump can deliver is characterized by two cu r ves in the t ypical pe r formance characteristics section. in pulse - skipping mode, if v in is between 100% and 110% of the regulated v out voltage, tg turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. this threshold current is set to approximately 6%, 4% or 3% of the maximum ilim current when the ilim pin is grounded, floating or tied to in t v cc , respectivel y . if the controller is programmed to burst mode operation under this same v in windo w , then tg remains off regardless of the inductor current. if the ovmode pin is grounded and v in rises above 110% of the regulated v out voltage in any mode, the controller turns on tg regardless of the inductor current. in burst mode operation, howeve r , the internal charge pump turns off if the chip is asleep. with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient tg voltage needed to keep the top mosfet completely on. t o prevent exces - sive power dissipation across the body diode of the top mosfet in this situation, the chip can be switched over to fo r ced continuous mode to enable the charge pump; a schottky diode can also be placed in parallel with the top mosfe t . power good the pgood pin is connected to an open drain of an internal n - channel mosfe t . the mosfet turns on and pulls the pgood pin low when the vfb pin voltage is not within 10% of the 1.2v reference voltage. the pgood pin is also pulled low when the corresponding run pin is low (shut down). when the vfb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a sou r ce of up to 6v (abs max). ove r voltage mode selection the ovmode pin is used to select how the l tc3769 operates during an ove r voltage event, defined as when the output feedback voltage (v fb ) is greater than 110% of its normal regulated point of 1.2 v . it is also used to determine the light - load mode of operation when the l tc3769 is synchronized to an external clock through the pllin/mode pin. the ovmode pin is a logic input that should normally be tied to in t v cc or grounded. alternativel y , the pin can be left floating, which allow a weak internal resistor to pull it down to ground. ovmode = in t v cc : an ove r voltage event causes the error amplifier to pull the ith pin lo w . in burst mode operation, this causes the l tc3769 to go to sleep and tg and bg are held off. in pulse - skipping mode, bg is held off and tg will turn on if the inductor current is positive. in fo r ced continuous mode, tg (and bg) will switch on and off as the l tc3769 will regulate the inductor current to a negative peak value (corresponding to ith = 0v) to discharge the output. when ovmode is tied to in t v cc , the l tc3769 operates in pulse - skipping mode when synchronized. in summa r y , with ovmode = in t v cc , the inductor cu r - rent is not allowed to go negative (reverse from output to input) except in fo r ced continuous mode, where it does reverse current but in a controlled manner with a regulated negative peak current. ovmode should be tied to in t v cc in applications where the output voltage may sometimes be above its regulation point (for example, if the output
3769f 14 fo r mor e ??e? ictry ? l tc3769 o pera t ion is a batte r y or if there are other power supplies driving the output) and no reverse current flow from output to input is desired. ovmode grounded or left floating: when ovmode is grounded or left floating, ove r voltage protection is enabled and tg is turned on continuously until the ove r voltage condition is cleared, regardless of whether burst mode operation, pulse - skipping mode, or fo r ced continuous mode is selected by the pllin/mode pin. this can cause large negative inductor currents to flow from the output to the input if the output voltage is higher than the input voltage. note however that in burst mode operation, the l tc3769 is in sleep during an ove r voltage condition, which disables t h e i n t e r n a l o sc ill a t o r a nd b oo s t - s w c h a r g e pu m p. s o the boos t - sw voltage may discharge (due to leakage) if the ove r voltage conditions persists indefinitel y . if boos t - sw discharges, then by definition tg would turn off. when ovmode is grounded or left floating, the l tc3769 operates in fo r ced continuous mode when synchronized. ovmode should be tied to ground or left floating in ci r - cuits, such as automotive applications, where the input voltage can often be above the regulated output voltage and it is desirable to turn on tg to ?pass through? the input voltage to the output. operation at low sense pin common mode v oltage the current comparator in the l tc3769 is powered directly from the sense + pin. this enables the common mode voltage of the sense + and sense ? pins to operate at as low as 2.3 v , which is below the uvlo threshold. figure 10 shows a typical application in which the controlle r? s vbias is powered from v out while the v in supply can go as low as 2.3 v . if the voltage on sense + drops below 2.3 v , the ss pin will be held lo w . when the sense voltage returns to the normal operating range, the ss pin will be released, initiating a new soft - start cycle. boost supply refresh and internal charge pump th e to p mosfe t drive r i s biase d fro m th e floatin g bootstrap capacito r , c b , whic h normall y recharge s durin g eac h cycle throug h a n externa l diod e whe n th e botto m mosfe t turns on. ther e ar e tw o consideration s fo r keepin g th e boost suppl y a t th e require d bia s level . durin g start - up , i f the botto m mosfe t is no t turne d o n withi n 200 s afte r uvlo goe s lo w , th e botto m mosfe t wil l b e fo r ce d t o tur n o n for ~400ns . thi s fo r ced refres h generate s enough boos t - sw voltag e t o allo w th e to p mosfe t read y t o b e full y enhanced instea d o f waitin g fo r th e initia l fe w cycle s t o charg e up. the r e i s a ls o a n i nterna l c ha rg e pu m p t ha t ke ep s t h e req uir ed bia s o n boos t . th e charg e pum p alway s operate s i n both fo r ce d continuou s mod e an d pulse - skippin g mode . i n burst mod e operation , th e charg e pum p i s turne d of f durin g sleep and enable d when th e chi p wakes up. the interna l charge pum p ca n normall y suppl y a chargin g curren t o f 55a.
3769f 15 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion r1 + r2 the t ypical application on the first page is a basic l tc3769 application ci r cuit. the l tc3769 can be configured to use either inductor dcr (dc resistance) sensing or a discrete sense resistor (r sense ) for current sensing. the choice between the two current sensing schemes is largely a design trade - off between cost, power consumption and accurac y . dcr sensing is becoming popular because it does not require current sensing resistors and is more powe r - efficient, especially in high current applications. howeve r , current sensing resistors provide the most accurate current limits for the controlle r . other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfe t s are selected. finall y , input and output capacitors are selected. sense + and sense ? pins the sense + and sense ? pins are the inputs to the cu r - rent comparators. the common mode input voltage range of the current comparators is 2.3v to 60 v . the current sense resistor is normally placed at the input of the boost controller in series with the inducto r . the sense + pin also provides power to the current com - parato r . it draws ~200a during normal operation. there is a small base current of less than 1a that flows into the sense ? pin. the high impedance sens e ? input to the current comparators allows accurate dcr sensing. filter components mutual to the sense lines should be placed close to the l tc3769, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cu r - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small - signal nodes. to sense filter, next to the controller v in inductor or r sense 3769 f01 figure 1. sense lines placement with inductor or sense resistor vbias v in sense + vbias v in sense + sense ? intv cc ltc3769 boost (optional) sense ? intv cc ltc3769 boost c1 r2 r1 dcr l inductor tg tg sw bg gnd v out 3769 f02a sw bg gnd place c1 near sense pins (r1 || r2) ? c1 = l dcr v out 3769 f02b r sense(eq) = dcr ? r2 (2a) using a resistor to sense current (2b) using the inductor dcr to sense current figure 2. t wo different methods of sensing current
3769f 16 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion d c r sense resistor current sensing a typical sensing ci r cuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the curren t comparato r has a maximu m threshold v sense(max) . when the ilim pin is grounded, floating or tied to in t v cc , the maximum threshold is set to 50m v , 75mv or 100m v , respectivel y . the current comparator threshold sets the peak of the inductor current, yielding a maximum average inductor current, i max , equal to the peak value less half the peak - to - peak ripple current, i l . t o calculate the sense resistor value, use the equation: v s e n s e ( m a x ) if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. t o properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc mete r , but the dcr tolerance is not always the same and varies with temperature. consult the manufacturers? data sheets for detailed information. using the inductor ripple current value from the induct - or value calculation section, the target sense resistor value is: r s e ns e = i m a x + i l 2 r s e n s e ( e q u i v ) v s e n s e ( m a x ) = i l i m a x + the actual value of i max depends on the required output current i out(max) and can be calculated using: v o u t 2 t o ensure that the application will deliver full load current over the full operating temperature range, choose the i m a x = i ou t ( m a x ) ? v i n minimum value for the maximum current sense threshold (v sense(max) ). when using the controller in low v in and ve r y high voltage output applications, the maximum inductor current and correspondingly the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for boost regulators operating at greater than 50% duty facto r . a cu r ve is provided in the t ypical pe r formance characteristics section to estimate this reduction in peak inductor current level depending upon the operating duty facto r . next, determine the dcr of the inducto r . where provided, use the manufacture r? s maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c. a conse r vativ e valu e fo r th e maximu m inducto r temperature (t l(max) ) is 100c. t o scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r s e n s e ( e q u i v ) inductor dcr sensing for applications requiring the highest possible efficiency r d = m a x a t t l ( m a x ) at high load currents, the l tc3769 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor can be less than 1m for high current inductors. in a high current application requiring such an inducto r , conduction loss through a sense resistor could reduce the efficiency by a few pe r cent compared to dcr sensing. c1 is usually selected to be in the range of 0.1f to 0.47 f . this fo r ces r1|| r2 to around 2k, reducing error that might have been caused by the sense ? pin ? s 1a current. the equivalent resistance r1|| r2 is scaled to the room temperature inductance and maximum dcr: r 1 || r 2 = l ( d c r a t 20 c ) ? c 1
3769f 17 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion o u t the sense resistor values are: r 1 = r 1 || r 2 ; r 2 = r 1 ? r d r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at v in = 1/2v out : p = ( v ou t ? v i n ) ? v i n l o s s _ r 1 r 1 ensure that r1 has a power rating higher than this value. if high efficiency is necessa r y at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resisto r , due t o th e extr a switchin g losse s incurre d throug h r1 . howeve r , dcr sensing eliminates a sense resisto r , reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor v alue calculation the operating frequency and inductor selection are in - terrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficienc y . a higher frequency generally results in lower efficiency because of mosfet gate charge and switching losses. also, at higher frequency the duty cycle of body diode conduction is highe r , which results in lower efficienc y . in addition to this basic trade - off, the effect of inductor value on ripple curren t and lo w curren t operatio n mus t als o b e considered. the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance or frequency and increases with higher v in : the inductor value also has seconda r y effects. the tra n - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. once the value of l is known, an inductor with low dcr and low core losses should be selected. power mosfet selection t wo external power mosfe t s must be selected for the l tc3769: one n - channel mosfet for the bottom (main) switch, and one n - channel mosfet for the top (synchro - nous) switch. the peak - to - peak gate drive levels are set by the in t v cc voltage. this voltage is typically 5.4v during start - up (see ext v cc pin connection). consequentl y , logic - level threshold mosfe t s must be used in most applications. pay close attention to the bv dss specification for the mosfe t s as well; many of the logic level mosfe t s are limited to 30v or less. selection criteria for the power mosfe t s include the on- resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge cu r ve usually provided on the mosfet manufacture r? s data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the cu r ve is approximately flat divided by the specified change in vds. this result is then multiplied by the ratio of the application applied vds to the gate charge cu r ve specified vds. when the ic v i n ? v i n ? is operating in continuous mode, the duty cycles for the i l = f ? l ? ? 1 ? v ? ? accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is i l = 0.3(i max ). the maximum i l occurs at v in = 1/2v out . top and bottom mosfe t s are given by: ma i n s w i t c h d ut y c yc l e = v ou t ? v i n v o u t s y nc hr onous s w i t c h d ut y c yc l e = v i n v o u t
3769f 18 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion ? i ? ( 1 + ? i ? ( 1 + 2 if the maximum output current is i out(max) the mosfet power dissipation at maximum output current is given by: although ceramic capacitors can be relatively tolerant of ove r voltage conditions, aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any p m a i n = ( v ou t v i n ) v o u t v 2 i n ou t ( m a x ) ) i o u t ( m a x ) possible ove r voltage transients that could apply excess stress to the input capacitors. the value of c in is a function of the sou r ce impedance, and ? r d s ( on ) + k ? v ou t 3 ? ? c mi ller ? f v i n in general, the higher the sou r ce impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty p = v i n syn c v o u t 2 ou t ( m a x ) ) ? r d s ( o n ) cycles can place great demands on the input suppl y , both in terms of dc current and ripple current. where is the temperature dependency of r ds(on) . the constant k, which accounts for the loss caused by reverse recove r y current, is inversely proportional to the gate drive current and has an empirical value of 1.7. bot h mosfe t s have i 2 r losse s whil e th e botto m n - channel equation includes an additional term for transition losses, which are highest at low input voltages. for high v in the high current efficiency generally improves with larger mosfe t s, while for low v in the transition losses rapidly i n a boos t converte r , th e outpu t ha s a discontinuou s current, so c out must be capable of reducing the output voltage ripple . th e effect s o f es r (equivalen t serie s resistance ) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple voltage due to charging and discharging the bulk capacitance in a single phase boost converter is given by: i ou t ( m a x ) ? ( v ou t ? v i n ( m i n ) ) increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficienc y . the v ripp le = c o u t v ? v ou t ? f synchronous mosfet losses are greatest at high input voltage when the bottom switch duty factor is low or dur - ing ove r voltage when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs t emperature cu r ve, but = 0.005/c can be used as an approximation for low voltage mosfe t s. c in and c out selection the input ripple current in a boost converter is relatively lo w (compare d wit h th e outpu t rippl e current) , because this curren t i s continuous . th e inpu t capacito r c i n voltag e rating should comfortably exceed the maximum input voltage. where c out is the output filter capacito r . the steady ripple due to the voltage drop across the esr is given by: v esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. d r y tantalum, special polyme r , aluminum electrolytic and ceramic capacitors are all available in su r face mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings (e.g., os - con and poscap).
3769f 19 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion a setting output v oltage the l tc3769 output voltage is set by an external feedback resisto r divide r carefull y place d acros s th e output , a s shown in figure 3. the regulated output voltage is determined by: c ss l tc3769 ss gnd 3769 f04 ? r b ? v ou t = 1. 2 v ? ? 1 + r ? ? figure 4. using the ss pin to program soft - start great care should be taken to route the vfb line away from noise sou r ces, such as the inductor or the sw line. also place the feedback resistor divider close to the vfb pin and keep the vfb node as small as possible to avoid noise pickup. v out l tc3769 r b vfb r a 3769 f03 figure 3. setting output v oltage soft - start (ss pin) the start - up of v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 1.2v reference, the l tc3769 regulates the vfb pin voltage to the voltage on the ss pin instead of 1.2 v . soft - star t i s enable d b y simpl y connectin g a capacito r from the ss pin to ground, as shown in figure 4. an internal 10a current sou r ce charges the capacito r , providing a linear ramping voltage at the ss pin. the l tc3769 will regulate the vfb pin (and hence, v out ) according to the voltage on the ss pin, allowing v out to rise smoothly from v in to its final regulated value. the total soft - start time will be approximately: in t v cc regulators the l tc3769 features two separate internal p - channel low dropout linear regulators (ldo) that supply power at the in t v cc pin from either the vbias supply pin or the ext v cc pin depending on the connection of the ext v cc pin. in t v cc powers the gate drivers and much of the l tc3769 ? s internal ci r cuit r y . the vbias ldo and the ext v cc ldo regulate in t v cc to 5.4v . each of these can s upp l y a t l ea s t 50 m a a nd m u s t b e b y p a ss e d t o g r ound with a minimum of a 4.7f ceramic capacito r . good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfe t s are being driven at high frequencies may cause the max i - mum junction temperature rating for the l tc3769 to be exceeded. the in t v cc current, which is dominated by the gate charge current, may be supplied by either the vbias ldo or the ext v cc ldo. when the voltage on the ex t v cc pin is less than 4.8 v , the vbias ldo is enabled. in this case, power dissipation for the ic is highest and is equal to vbias ? i in t vcc . the gate charge current is dependent on operating frequenc y , as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, at 70c ambient temperature, the l tc3769 in t v cc current is limited to less than 19ma in the qfn package from a 60v vbias supply t s s = c s s ? 1. 2 v 1 0 a when not using the ext v cc supply: t j = 70c + (19ma)(60v)(47c/w) = 125c
3769f 20 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion in the tssop package, the in t v cc current is limited to less than 24ma from a 60v supply when not using the ext v cc supply: t j = 70c + (24ma)(60v)(38c/w) = 125c t o prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = in t v cc ) at maximum v in . when the voltage applied to ex t v cc rises above 4.8 v , the v in ldo is turned off and the ext v cc ldo is enabled. the ext v cc ldo remains on as long as the voltage applied to ext v cc remains above 4.55 v . the ex t v cc ldo attempts to regulate the in t v cc voltage to 5.4 v , so while ex t v cc is less than 5.4 v , the ldo is in dropout and the in t v cc voltage is approximately equal to ext v cc . when ex t v cc is greater than 5.4 v , up to an absolute maximum of 14 v , in t v cc is regulated to 5.4 v . significant thermal gains can be realized by powering in t v cc from an external suppl y . t ying the ex t v cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to 75c in a qfn package: t j = 70c + (19ma)(5v)(47c/w) = 75c and from 125c to 75c in the tssop package: t j = 70c + (24ma)(5v)(38c/w) = 75c the following list summarizes possible connections for ex t v cc : ex t v c c g r ound e d . t h i s w il l c a u s e in t v c c t o b e po w e r e d fro m th e interna l 5.4 v regulato r resultin g i n a n efficiency penalty at high v bias voltages. ex t v cc connected to an external suppl y . if an external supply is available in the 5v to 14v range, it may be used to provide powe r . ensure that ext v cc is always lower than or equal to vbias. t opside mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfe t . capacitor c b in the block diagram is charged though external diode d b from in t v cc when the sw pin is low . when the topside mosfet is to be turned on, the driver places the c b voltage across the gate and sou r ce of the desired mosfe t . this enhances the mosfet and turns on the topside switch. the switch node voltage, s w , rises to v out and the boost pin follows. with the topside mosfet on, the boost voltage is above the output voltage: v boost = v out + v in t vcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external diode d b must be greater than v out(max) . the external diode d b can be a schottky diode or silicon diode, but in either case it should have low leakage and fast recove r y . pay close attention to the reverse leakage at high temperatures, where it generally increases substantiall y . the topside mosfet driver includes an internal charge pump that delivers current to the bootstrap capacitor from the boost pin. this charge current maintains the bias voltage required to keep the top mosfet on continuously during dropout/ove r voltage conditions. the schottky/ silicon diode selected for the topside driver should have a reverse leakage less than the available output current the charge pump can suppl y . cu r ves displaying the available charge pump current under different operating conditions can be found in the t ypical pe r formance characteristics section. a leaky diode d b in the boost converter can not only prevent the top mosfet from fully turning on but it can also completely discharge the bootstrap capacitor c b and create a current path from the input voltage to the boost pin to in t v cc . this can cause in t v cc to rise if the diode leakage exceeds the current consumption on in t v cc . this is particularly a concern in burst mode operation
3769f 21 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion frequency (khz) where the load on in t v cc can be ve r y small. the external schottky or silicon diode should be carefully chosen such that in t v cc never gets charged up much higher than its normal regulation voltage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on- chip (such as an in t v cc short to ground), the overtemperature shutdown ci r cuit r y will shut down the l tc3769. when the junction temperature exceeds approximately 170c, the overtemperatur e ci r cuit r y disable s th e in t v c c ldo , causing the in t v cc supply to collapse and effectively shut down the entire l tc3769 chip. once the junction temperature drops back to approximately 155c, the in t v cc ldo turns back on. long term overstress (t j > 125c) should be avoided as it can degrade the per formance or shorten an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacito r , c lp , holds the voltage at the vco input. 1000 900 800 700 600 500 400 300 200 100 the life of the part. 0 15 25 35 45 55 65 75 85 95 105 115 125 since the shutdown may occur at full load, beware that freq pin resistor (kfi) 3769 f05 the load current will result in high power dissipation in the body diodes of the top mosfe t s. in this case, the pgood output may be used to turn the system load off. phase - locked loop and frequency synchronization the l tc3769 has an internal phase - locked loop (pll) comprised of a phase frequency detecto r , a lowpass filter and a voltage - controlled oscillator (vco). this allows the turn - on of the bottom mosfet to be locked signal applied to 180 degrees out - of - phase to the rising edge of the external clock. the phase detector is an edge - sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillato r ? s frequenc y , f osc , the n curren t i s sou r ce d contin u - ously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuousl y , pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sou r ces turn on for figure 5. relationship between oscillator frequency and resistor v alue at the freq pin t ypicall y , th e externa l cloc k (o n th e pllin/mod e pin ) input high threshold is 1.6 v , while the input low threshold is 1.2 v . note that the l tc3769 can only be synchronized to an external clock whose frequency is within range of the l tc3769 ? s internal vco, which is nominally 55khz to 1mhz . thi s i s guarantee d t o b e betwee n 75khz an d 850khz. rap id phas e locking c an be achieved by using the f req pin to set a free - running frequency near the desired synchro - nization frequenc y . the vco ? s input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchro - nization. although it is not required that the free - running frequency be near external clock frequenc y , doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks.
3769f 22 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion o u t ( m a x ) t able 1 summarizes the different states in which the freq pin can be used. t able 1. freq pin pllin/mode pin frequency 0v dc v oltage 350khz int v cc dc v oltage 535khz resistor dc v oltage 50khz to 900khz any of the above external clock phase locked to external clock minimum on - t ime considerations minimum on - time, t on(min) , is the smallest time duration that the l tc3769 is capable of turning on the bottom mosfe t . it is determined by internal timing delays and the gate charge required to turn on the top mosfe t . low duty cycle applications may approach this minimum on- time limit. in fo r ced continuous mode, if the duty cycle falls below what can be accommodated by the minimum on - time, the controller will begin to skip cycles but the output will continue to be regulated. more cycles will be skipped when v in increases. once v in rises above v out , the loop keeps the top mosfet continuously on. the minimum on- time for the l tc3769 is approximately 110ns. efficiency considerations although all dissipative elements in the ci r cuit produce losses, five main sou r ces usually account for most of the losses in l tc3769 ci r cuits: 1) ic vbias current, 2) in t v cc regulator current, 3) i 2 r losses, 4) bottom mosfet trans i - tion losses, 5) body diode conduction losses. 1. the vbias current is the dc supply current given in the electrica l characteristic s table , whic h exclude s mosfet driver and control currents. vbias current typically results in a small (<0.1%) loss. 2. in t v cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfe t s. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from in t v cc to ground. the resulting dq/dt is a current out of in t v cc that is typically much larger than the control ci r cuit current. in continuous mode, i ga techg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfe t s. 3. dc i 2 r losses. these arise from the resistances of the mosfe t s , sensin g resisto r , inducto r an d p c boar d traces and cause the efficiency to drop at high output currents. 4. t ransition losses apply only to the bottom mosfet(s), and become significant only when operating at low input voltages. t ransition losses can be estimated from: the pe r cent efficiency of a switching regulator is equal to t r a n s i t i on los s = ( 1. 7 ) v ou t 3 ? i ? c r s s ? f the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the greatest improvement. pe r cent efficiency can be expressed as: %efficiency = 100% ? (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a pe r cen t - age of input powe r . v i n 5. body diode conduction losses are more significant at higher switching frequenc y . during the dead time, the loss in the top mosfet is i out ? v ds , where v ds is around 0.7 v . at higher switching frequenc y , the dead time becomes a good pe r centage of switching cycle and causes the ef - ficiency to drop.
3769f 23 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion other hidden losses, such as copper trace and internal batte r y resistances , can accoun t fo r a n additiona l efficiency degradation in portable systems. it is ve r y important to include these system - level losses during the design phase. checking t ransient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , generating the feedback error signal that fo r ces the regulator to adapt to the current change and return v out to its steady - state value. during this recove r y time v out can be monitored for excessive ove r - shoot or ringing, which would indicate a stability problem. o p ti - loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavio r , but it also provide s a d c couple d an d ac filtere d close d loo p response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the pe r centage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in the figure 10 ci r cuit will provide an adequate starting point for most applications. the ith series r c - c c filter sets the dominant pole - zero loop compensation. the values can be modified slightly to optimize transient response once the final pc layout is complete and the particular output capacitor type and value have been determined. the output capacitors must b e selecte d becaus e th e variou s type s an d value s determine the loop gain and phase. an output current pulse of 20% to 80% of full - load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet and load resistor directly across the output capacitor and driving the gate with an a p - propriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by d e - creasing c c . if rc is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed - loop system and will demonstrate the actual overall supply per formance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delive r y of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickl y . if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus, a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in = 12v (nominal), v i n = 22v (max) , v ou t = 24 v , i out(max ) = 4a , v sense(max ) = 75m v , and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. t ie the freq pin to gnd, generat -
3769f 24 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion o u t ing 350khz operation. the minimum inductance for 30% ripple current is: pc board layout checklist when laying out the printed ci r cuit board, the following v i n ? v i n ? checklist should be used to ensure proper operation of i l = f ? l ? ? 1 ? v ? ? the largest ripple happens when v in = 1/2v out = 12 v , where the average maximum inductor current is: v o u t the ic. these items are also illustrated graphically in the layout diagram of figure 6. figure 7 illustrates the current waveform s presen t i n th e synchronou s regulato r operating i n th e continuou s mode . chec k th e followin g i n you r layout: i m a x = i out ( m a x ) ? v i n = 8 a 1. put the bottom n - channel mosfet mbot and the top n- channel mosfet mtop1 in one compact area with a 6.8h inductor will produce a 31% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 9.25a. the r sense resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: r 75 m v = 0.00 8 s e n s e 9.25 a choosing 1% resistors: r a = 5k and r b = 95.3k yields an output voltage of 24.072 v . the power dissipation on the top side mosfet can be easily estimated. choosing a vishay si7848bdp mos - fe t result s in : r ds(on ) = 0.012 , c mille r = 150p f . at maximum input voltage with t (estimated) = 50c: ( 2 4 v ? 1 2 v ) 2 4 v c out . 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c in t vcc must return to the combined c out ( ? ) terminals. the path formed by the bottom n - channel mosfet and the capacitor should have short leads and pc trace lengths. the output capacitor ( ? ) terminals should be connected as close as possible to the sou r ce terminals of the bottom mosfe t s. 3. does the l tc3769 vfb pin ? s resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground and placed close to the vfb pin. the feedback resistor connections should not be along the high cu r - rent input feeds from the input capacitor(s). 4. are the sense ? and sense + leads routed together with p m a i n = ( 1 2 v ) 2 ? ( 4 a ) 2 minimu m p c trac e spacing ? th e filte r capacito r between sense + and sense ? should be as close as possible ? [ 1 + ( 0.00 5 ) ( 50 c ? 25 c ) ] ? 0.012 + ( 1. 7 ) ( 2 4v ) 3 4 a ( 15 0 p f ) ( 35 0 k h z ) = 0.8 4 w 1 2 v c out is chosen to filter the square current in the output. the maximum output current peak is: to the ic. ensure accurate current sensing with kelvin connections at the sense resisto r . 5. is the in t v cc decoupling capacitor connected close to the ic, between the in t v cc and the power ground pins? this capacitor carries the mosfet drivers? cu r - rent peaks. an additional 1f ceramic capacitor placed ? 31% ? i out ( p e a k ) = 8 ? ? ? 1 + 2 ? ? = 9.3 a immediately next to the in t v cc and gnd pins can help improve noise pe r formance substantiall y . a low esr (5m) capacitor is suggested. this capacitor will limit output voltage ripple to 46.5mv (assuming esr dominates the ripple).
3769f 25 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion sense + sense ? pgood v pullup sw l1 r sense l tc3769 tg ovmode c b f in freq pllin/mode run vfb ith ss boost bg vbias gnd in t v cc m1 + m2 + gnd v in v out 3769 f06 figure 6. recommended printed circuit layout diagram v in r sense l1 sw v out r in c in c out r l 3769 f07 bold lines indicate high switching current. keep lines to a minimum length figure 7. branch current w aveforms
3769f 26 fo r mor e ??e? ictry ? l tc3769 a pplica t ion s in f or m a t ion 6. keep the switching node (sw), top gate node (tg) and boost node (boost) away from sensitive small - signal nodes . al l o f thes e node s have ve r y larg e and fas t moving signals and, therefore, should be kept on the output side of the l tc3769 and occupy a minimal pc trace area. 7. use a modified ?star ground? technique: a low impe d - ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie - ins for the bottom of the in t v cc decouplin g capacito r , th e botto m o f th e voltag e feedback resistive divider and the gnd pins of the ic. pc board layout debugging it is helpful to use a dc - 50mhz current probe to monitor the current in the inductor while testing the ci r cuit. moni - tor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage. check for proper per formance over the operating voltage and current range expected in the application. the frequency of operation should be main - tained over the input voltage range down to dropout and until the output load drops below the low current opera - tion threshold ? typically 10% of the maximum designed current level in burst mode operation. t h e du t y cyc l e p e r c e n t a g e s hou l d b e m a i n t a i n e d fr o m cyc l e to cycle in a well designed, low noise pcb implement a - tion. v ariation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. ove r compensa - tion of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation with high duty cycle. check the operation of the unde r voltage lockout ci r cuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boos t , s w , tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. an embarrassing problem which can be missed in an oth - e r wise properly working switching regulato r , results when the current sensing leads are hooked up backwards. the output voltage under this improper hook - up will still be maintained, but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistor ? don?t wor r y , the regulator will still maintain control of the output voltage.
l tc3769 typica l a pplica t ions 3769f 27 fo r mor e ??e? ictry ? cc i lim ext v vbias sense + l tc3769 sense ? r sense 4mfi c in 22f v in 5v to 24v c ith 15nf c ss 0. 1 f r ith 12.1k ovmode pllin/mode run freq ss ith tg sw boost bg c b 0. 1 f d l 3.3h mtop mbot c ou t a + 22f 4 c outb 150f v out 24v 5a* c itha 100pf r a 12.1k r s 232k vfb in t v cc gnd pgood 100k c int 4.7f c in , c ou t a : tdk c4532x5r1e226m c outb : suncon 35hvh150m d: bas140w l: pulse p a1494.362nl mbo t , mtop: renesas rjk0452, rjk0453 3769 f08 *when v in < 8 v , maximum load current av ailable is reduced. when v in > 24 v , v out follows v in . figure 8. high efficiency 24v boost converter vbias sense + v in i lim ext v l tc3769 cc sense ? r sense 4mfi c in 22f 5v to 28v c ith 15nf c ss 0. 1 f r ith 8.66k ovmode pllin/mode run freq ss ith tg sw boost bg c b 0. 1 f d l 3.3h mtop mbot c ou t a + 22f 4 c outb 150f v out 28v 4a* c itha 220pf r a 12.1k r s 261k vfb in t v cc gnd pgood 100k c int 4.7f c in , c ou t a : tdk c4532x7r1h685k c outb : suncon 63ce220kx d: bas140w l: pulse p a1494.362nl mbo t , mtop: renesas h a t2169h 3769 f09 *when v in < 8 v , maximum load current av ailable is reduced. when v in > 28 v , v out follows v in . figure 9. high efficiency 28v boost converter
l tc3769 3769f 28 fo r mor e ??e? ictry ? efficiency (%) typica l a pplica t ions i lim vbias sense + l tc3769 r sense 2m? c in a + 10f 2 c inb 50f 2 v in 5v to 60v s t a r t - up vo l t age oper a tes through transients down to 2.3v c ith 10nf c ss 0. 1 f r ith ex t v cc ovmode run freq ss sense ? tg sw boost c b 0. 1 f l 1.3h mtop c ou t a + 10f 3 c outb 56f 2 v out * 10v 5a c itha 820pf 4.75k ith bg in t v cc d c int mbot r a 64.9k r b 475k vfb gnd pllin/mode pgood 100k 4.7f l: w r th 7443551130 mbo t , mtop: infineon bsc028n06l53 d: bas170w *when v in > 10v , v out follows v in . c ina , c ou t a : grm32er71j106ka12l c inb , c outb : suncon 63hvh56m 3769 f10 figure 10. high efficiency 10v boost converter i lim vbias sense + l tc3769 c in v in 8v to 24v 41.2k c ss 0. 1 f ex t v cc ovmode run freq ss sense ? tg sw c1 0. 1 f r s2 53.6k 1% c b r s1 26.1k 1% l 10.2h mtop 22f c ou t a + c outb v out 24v* 4a 100 98 96 94 v in = 12v v in = 9v v in = 6v c ith 15nf r a 12.1k r ith 8.66k c itha 220pf ith boost bg in t v cc gnd pllin/mode 0. 1 f d c int 4.7f mbot 22f 4 220f 92 90 88 86 0 1 2 3 4 5 6 r b 232k vfb pgood 100k output current (a) 3769 f11b c1: tdk c1005x7r1c104k c in , c ou t a : tdk c4532x5r1e226m c outb : suncon, 50ce220ax l: pulse p a2050.103nl mbo t , mtop: renesas rjk0305 d: infineon bas140w 3769 f11a figure 11. high efficiency 24v boost converter with inductor dcr current sensing
l tc3769 typica l a pplica t ions 3769f 29 fo r mor e ??e? ictry ? vbias sense + v in l tc3769 ext v cc r sense 6mfi c in 10f 5v to 60v 47.5k c ss 0. 1 f c ith 10nf r ith 24.9k c itha 100pf 12.1k 1% 232k 1% ovmode pllin/mode run freq ss ith vfb sense ? tg sw boost bg i lim in t v cc gnd pgood 100k l 6.8h d mbot c int 4.7f 2 c ou t a + 10f c outb 56f 2 v out 24v* 2a c in , c ou t a : mur at a grm32er71j106ka12l c outb : suncon 63hvh56m d: diodes inc b360 l: coilcra f t xal1010 6.8h mbo t : infineon bsc100no6ls *when v in > 24v , v out follows v in . 3769 f12 figure 12. low i q nonsynchronous 24v/2a boost converter v in 18v to 32v ext v vbias sense + l tc3769 cc 4mfi 4.7f 3 + 15nf 12.1k 0. 1 f 12.1k 100pf 232k ovmode ilim pllin/mode run freq ss ith vfb sense ? tg sw bg boost in t v cc gnd 4.7f ? l1 4.7f d1 (4) l1 m1 33f 4.7f 5 + 220f 2 v out 24v 2.5a 3769 f13 l1: coi l tronics, versa p ac vph5 - 0067 - r d1: central semiconductor, cmsh5 - 60 m1: infineon bsc0281106ls3 figure 13. low i q 24v out sepic converter
l tc3769 3769f 30 fo r mor e ??e? ictry ? (4 sides) pin 1 top mark (note 6) packag e descrip t ion please refer to http://www.ictry.cn/ic/124.html for the most recent package drawings. uf package 24 - lead plastic qfn (4mm 4mm) (reference ltc dwg # 05- 08 - 1697 rev b) 0.70 0.05 4.50 0.05 3.10 0.05 2.45 0.05 (4 sides) package outline 0.25 0.05 0.50 bsc recommended solder pad pitch and dimensions 4.00 0.10 bottom view ? exposed pad 0.75 0.05 r = 0.115 pin 1 notch r = 0.20 typ or 0.35 45 chamfer typ 23 24 0.40 0.10 1 2 2.45 0.10 (4 - sides) note: 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b 0.25 0.05 0.50 bsc 1. drawing proposed to be made a jedec package outline mo - 220 variation (wggd - x) ? to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package

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